1. Technical Field
The present invention relates to a semiconductor circuit, and more particularly, to an impedance control signal generation circuit and an impedance control method of a semiconductor circuit.
2. Related Art
In a semiconductor circuit, the impedance of a data input/output driver has a value different from the original target value according to a variation in PTV (process, voltage, or temperature).
Accordingly, it is important to constantly maintain the impedance of the data input/output driver regardless of the PTV variation.
In the semiconductor circuit, the impedance of the data input/output driver is controlled according to an impedance control signal generated through an impedance control signal generation circuit.
Referring to FIG. 1, an impedance control signal generation circuit 1 according to the conventional art includes an impedance control signal generation unit 10 and a storage unit 20.
The impedance control signal generation unit 10 generates impedance control signals PCODEi<0:N> in response to an external command CMD.
The external command CMD may be generated in an initial system operation or an auto-refresh operation.
The impedance control signal generation unit 10 performs auto-calibration (ACAL) for a predetermined time period in response to the external command CMD.
The impedance control signal generation unit 10 activates an internal signal (that is, a calibration end signal CALEND) for defining the end of initial auto-calibration which is performed according to the external command CMD generated in the initial system operation.
The storage unit 20 latches and outputs the impedance control signals PCODEi<0:N> in response to an update pulse signal PULSE_UPD.
The update pulse signal PULSE_UPD may be generated in the process of auto-calibration which is performed according to the external command CMD generated in the auto-refresh operation.
The impedance control signals PCODEi<0:N> outputted from the storage unit 20 are provided to a data input/output driver, so that the impedance of the data input/output driver is calibrated.
The impedance control signal generation circuit 1 according to the conventional art latches and outputs the impedance control signals PCODEi<0:N>, which have been generated by the impedance control signal generation unit 10, whenever the update pulse signal PULSE_UPD is generated.
When the impedance control signals PCODEi<0:N> have an abnormal value out of a normal range, the impedance of the data input/output driver may also have an abnormal value.
Specifically, since the operation of the impedance control signal generation unit 10 in the auto-refresh operation is significantly affected by power noise, it is highly probable that an impedance control signal generated at a corresponding time point will have an abnormal value.